Conference paper
Long-term power minimization of dual-νΤ CMOS circuits
Suhwan Kim, Youngsoo Shin, et al.
ASIC/SOC 2002
This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described. © 1985 IEEE
Suhwan Kim, Youngsoo Shin, et al.
ASIC/SOC 2002
Sang H. Dhong, Nicky Chau-Chun Lu, et al.
IEEE Journal of Solid-State Circuits
Hu H. Chao, Robert H. Dermard, et al.
ISSCC 1981
Walter H. Henkels, Nicky C. C. Lu, et al.
IEEE T-ED