IBM J. Res. Dev

Editorial

01 May 2020

Preface: Summit and Sierra Supercomputers

Conference paper

Chip-level integration: The new frontier for microprocessor architecture

Jaime H. Moreno

SPAA 2006

Poster

Multi-scale Simulations Toolkit for Inertial Fusion Energy

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ISC 2024

Conference paper

Validation of Turandot, a fast processor model for microarchitecture exploration

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IEEE International Performance, Computing and Communications Conference, Proceedings 1999

Conference paper

Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling

C. J. Penny, Koichi Motoyama, et al.

IEDM 2022

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