Pure nodal analysis for efficient on-chip interconnect model order reduction

This paper described a model-order reduction (MOR) method based on a novel pure-nodal analysis formulation (PNA) which permits the use of symmetric, positive-definite Cholesky solvers for all circuit topologies. Moreover, frequently occurring special cases, e.g., inductor-resistor tree structures result in particular types of matrices that are solved by an even faster linear time algorithm. The model order reduction algorithms also uses symmetric-Lanczos iteration and nonstandard inner-products for generating the Krylov subspace basis. Its efficiency is supported by a wide range of industrial examples. © 2011 IEEE.