Reconfigurable systems and flexible programming for hardware design, verification and software enablement for system-on-a-chip architectures

Abstract

In this paper we provide a detailed description of a Field Programmable Gate Array (FPGA) based reconfigurable system which has been used in the development of a System on a Chip (SoC) processor and corresponding applications targeted for network computing appliances. The complexity of the processor, in terms of number of hardware threads (64), integrated on chip accelerators and network interfaces, combined with time to market requirements of the final system necessitated hardware verification and software development on pre-silicon systems that provided a high degree of architecture fidelity, reasonable time to completion for verification tests, and sufficient diagnosis tools for root cause analysis from processor logic to application design. To meet these requirements, we developed an FPGA based emulator which actually implemented the combined chip logic function by mapping it to FPGA equivalent gate functions. This system has the advantage over other simulation environments in that it has actual chip logic that can be executed at "real world speeds" e.g. MHz, rather than the traditional HDL simulators which are typically executed at 10 or 100's of KHz. Additional flexibility in terms of system verification, analysis and application development was provided by the development of a library OS based programming environment, Bare Metal Application (BMA), complimentary to both the FPGA based system as well as the actual silicon. The main contribution of this work was the development of a reconfigurable and flexible simulation system, both hardware and software which, to the best of our knowledge, provided the first heterogeneous multipurpose environment for silicon and software validation on a system with both general purpose cores and on board accelerators. © 2011 IEEE.