R.S. Tsay, Juergen Koehl
DAC 1991
An efficient system timing verification approach that employs latch graph representation is reported. It is a general approach that can handle most blocking schemes. Both early and late mode timing constraints are considered. The tool generates a detailed stack report to help designers identify where and how much the correction should be in case of violations. The algorithm has been implemented and tested on several real designs. An example with 1926 latches and dense interconnections is verified in 0.62 s.
R.S. Tsay, Juergen Koehl
DAC 1991
R.S. Tsay, S.C. Chang, et al.
Annual ASIC Conference and Exhibit 1992
G. Vijayan, R.S. Tsay
ICCAD 1990
R.S. Tsay
ICCAD 1991