Scalable Physical Design for Many-Accelerator SoCs

ESP, an open-source platform for the agile design of heterogeneous systems-on-chip (SoCs), has been a valuable tool that has enabled researchers in both academia and industry to conceptualize, design and prototype several domain-specific SoCs. In this paper, we highlight some of the ASICs that were designed using the ESP and their key architecture and circuit-level innovations. These ASICs were targeted for application domains ranging from connected autonomous vehicles to secure and resilient AI and were designed and manufactured in different technology nodes. We describe our experiences in the design and development of these chips and provide lessons learned that could prove valuable to researchers in the architecture, circuit, and design automation communities.