SPEED ENHANCEMENTS AND KEY DESIGN ASPECTS OF CHARGE BUFFERED LOGIC.

Abstract

The charge-buffered logic concept significantly reduces the dc power of bipolar logic, yet enables high-speed operation. Speed enhancements accomplished by improved PNP characteristics and by advancements in circuit design are discussed. Key design aspects and speed-enhancement techniques have been verified by experimental hardware. Despite conservative process parameters, a minimum delay time of 800 ps has been measured. Based on recently published advanced technologies, the potential of less than 300-ps gate delay at less than 10 mu W dc power has been projected.