Kanak Agarwal, Eric Rozner, et al.
SIGCOMM 2014
The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extreme. Copyright 2006 ACM.
Kanak Agarwal, Eric Rozner, et al.
SIGCOMM 2014
Rouwaida Kanj, Rajiv Joshi, et al.
DAC 2012
Rouwaida Kanj, Rajiv Joshi, et al.
VLSI Design
Hamed F. Dadgour, Rajiv V. Joshi, et al.
DAC 2006