The dawn of 22nm era: Design and CAD challenges

Abstract

Technology scaling clearly has been the driver of semiconductor and thereby EDA industry. In the semiconductor industry today, 45nm CMOS designs are in full production and 32nm design rules and infrastructure are already in place for designs starting later this year. It will not be long before the beat of 22nm will be upon us. Due to ever increasing cost of doing design, design productivity and more specifically, cost of design has become a major bottleneck in large scale design projects. Due to this cost crunch, automated synthesis techniques have been becoming increasingly important and this is bound to become a major trend going into 22nm for high performance SoCs. In addition, in 22nm and beyond, 3D IC technology has the potential of easing the system performance challenge problem. In order to exploit the full potential of 3D technology, new challenges in the area of physical design, thermal analysis, system level design and analysis need to be addressed. 3D interconnects have the potential of reducing critical paths delays significantly, which are typically between memory and the interfacing logic. In addition, now that the physical limits are beginning to impact scaling, the question is: how can we cost effectively design with complicated technology requirements presented by 22nm node and how the design automation community can help to achieve this goal? What are the challenges at 22nm and what would design look like going into 22nm and beyond? In this paper, we will focus on the major design and CAD challenges associated with 22nm and beyond. © 2010 IEEE.