Steven C. Chan, Phillip J. Restle, et al.
IEEE Journal of Solid-State Circuits
This paper presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-μm CMOS technology.
Steven C. Chan, Phillip J. Restle, et al.
IEEE Journal of Solid-State Circuits
Joseph Zuckerman, Martin Cochet, et al.
IEEE Journal of Solid State Circuits
Eugene J. O'Sullivan, Naigang Wang, et al.
PRiME/ECS Meeting 2012
Tobias Webel, Phillip J. Restle, et al.
ISSCC 2025