Clock tree and power grid design > 1 GHz
Phillip J. Restle, Albert Ruehli, et al.
ADMETA 2000
This paper presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-μm CMOS technology.
Phillip J. Restle, Albert Ruehli, et al.
ADMETA 2000
Steven C. Chan, Kenneth L. Shepard, et al.
ICCD 2003
Noah Sturcken, Eugene J. O'Sullivan, et al.
IEEE JSSC
Dieter F. Wendel, Ron Kalla, et al.
IEEE Journal of Solid-State Circuits