Daniel Brand, Vijay S. Iyengar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A protocol verifier using symbolic execution has been designed and implemented as part of a general verifier (oriented towards microcode). This part describes how this method works for communication protocols involving timing assumptions, state changes depending on message contents, unreliable medium, an arbitrary number of communicating processes, etc. The method can detect design errors such as deadlock and tempo-blocking; in addition the user can add his own assertions to express other desired properties. © 1978.
Daniel Brand, Vijay S. Iyengar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Daniel Brand, Tsutomu Sasao
IEEE TC
Daniel Brand, Pitro Zafiropulo
Journal of the ACM
Daniel Brand
ACM SIGPLAN Notices