Symbolic simulation for correct machine design
William C. Carter, William H. Joyner, et al.
DAC 1979
A protocol verifier using symbolic execution has been designed and implemented as part of a general verifier (oriented towards microcode). This part describes how this method works for communication protocols involving timing assumptions, state changes depending on message contents, unreliable medium, an arbitrary number of communicating processes, etc. The method can detect design errors such as deadlock and tempo-blocking; in addition the user can add his own assertions to express other desired properties. © 1978.
William C. Carter, William H. Joyner, et al.
DAC 1979
Chia-Yu Chen, Jungwook Choi, et al.
AAAI 2018
M. Cho, Daniel Brand
ICML 2017
Daniel Brand, Reinaldo A. Bergamaschi, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems