Abstract
Checkpoint and rollback recovery is a technique that allows a system to tolerate a failure by periodically saving the entire state and if an error is detected, rolling back to the prior checkpoint. This paper presents a technique that embeds the support for checkpoint and rollback recovery directly into the virtual memory translation hardware. The scheme is general enough to be implemented on various scopes of data such as a portion of an address space, a single address space or multiple address spaces. The technique can provide a very high performance scheme for implementing checkpoint and rollback recovery. We have analyzed the performance of the scheme using a trace driven simulation. The overhead is a function of the interval between checkpoints and becomes very small for intervals greater than 106 references. However, the scheme is shown to be feasible for intervals as small as 1000 references under certain conditions. © 1992 IEEE