Frank R. Libsch, S.C. Lien
IBM J. Res. Dev
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Frank R. Libsch, S.C. Lien
IBM J. Res. Dev
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