Anupam Gupta, Viswanath Nagarajan, et al.
Operations Research
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Anupam Gupta, Viswanath Nagarajan, et al.
Operations Research
Alfonso P. Cardenas, Larry F. Bowman, et al.
ACM Annual Conference 1975
John M. Boyer, Charles F. Wiecha
DocEng 2009
S. Sattanathan, N.C. Narendra, et al.
CONTEXT 2005