A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFETGain KimLukas Kullet al.2019A-SSCC 2019
30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFETGain KimLukas Kullet al.2019ISSCC 2019
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline ReceiverGain KimLukas Kullet al.2018ISCAS 2018