A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2014
- ISSCC 2014
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44 results for Yusuf Leblebici
A 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- IEEE JSSC
Integration of intra chip stack fluidic cooling using thin-layer solder bonding
- Yassir Madhour
- Michael Zervas
- et al.
- 2013
- 3DIC 2013
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- VLSI Circuits 2013
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- ISSCC 2013
Surface-tension-driven multi-chip self-alignment techniques for heterogeneous 3D integration
- Fengda Sun
- Yusuf Leblebici
- et al.
- 2011
- ECTC 2011
Pin-shape assessment for interlayer-cooled chip stacks with periodic boundary condition modeling
- Gözde Töral
- Roland Bender
- et al.
- 2010
- THERMINIC 2010
Heat-removal performance scaling of interlayer cooled chip stacks
- Thomas Brunschwiler
- Stephan Paredes
- et al.
- 2010
- ITherm 2010
Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks
- T. Brunschwiler
- S. Paredes
- et al.
- 2009
- 3DIC 2009
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology
- Thomas Liechti
- Armin Tajalli
- et al.
- 2008
- APCCAS 2008