22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
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9 results for Matthew A. Smalley
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- Q. Liu
- Frederic Monsieur
- et al.
- 2011
- VLSI Technology 2011
Reducing time dependent line to line leakage following post CMP clean
- Donald F. Canaperi
- Satyavolu S. Papa Rao
- et al.
- 2010
- MRS Online Proceedings Library
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- VLSI Technology 2009
Copper contact metallization using Ru-based barrier liners for 45 nm and 32 nm nodes: Reliability and device performance
- Soon-Cheon Seo
- Chih-Chao Yang
- et al.
- 2008
- ADMETA 2008
Copper contact metallization for 22 nm and beyond
- Soon-Cheon Seo
- Chih-Chao Yang
- et al.
- 2009
- IITC 2009
A comparative study of ceria-based and silica-based slurries for 32 nm shallow trench isolation chemical mechanical planarization
- Jason E. Cummings
- Matthew D. Smalley
- et al.
- 2008
- CMP-MIC 2008