High-density silicon carrier transmission line design for chip-to-chip interconnects
- Xiaoxiong Gu
- Lavanya Turlapati
- et al.
- 2011
- EPEPS 2011
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33 results for Timothy O. Dickson
A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS
- Jonathan E. Proesel
- Timothy O. Dickson
- 2011
- VLSI Circuits 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011
A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS
- Byungsub Kim
- Yong Liu
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
- Timothy O. Dickson
- John F. Bulzacchelli
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
- John F. Bulzacchelli
- Timothy O. Dickson
- et al.
- 2009
- ISSCC 2009
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
- Yong Liu
- Byungsub Kim
- et al.
- 2009
- ISSCC 2009
A 12-Gb/s 11-mW half-rate sampled 5-tap decision feedback equalizer with current-integrating summers in 45-nm SOI CMOS technology
- Timothy O. Dickson
- John F. Bulzacchelli
- et al.
- 2008
- VLSI Circuits 2008
A 2-GHz direct sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL
- T. Chalvatzis
- T.O. Dickson
- et al.
- 2007
- VLSI Circuits 2007
Low-power circuits for a 2.5-V, 10.7-to-86-Gb/s serial transmitter in 130-nm SiGe BiCMOS
- Timothy O. Dickson
- Sorin P. Voinigescu
- 2007
- IEEE Journal of Solid-State Circuits