A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
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27 results for Michael P. Beakes
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
- Filipp Akopyan
- Jun Sawada
- et al.
- 2015
- IEEE TCADIS
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
- John F. Bulzacchelli
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
- Troy Beukema
- Michael Sorna
- et al.
- 2005
- IEEE Journal of Solid-State Circuits
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution
- Peter H. Baechtold
- Michael P. Beakes
- et al.
- 2001
- IEEE Journal of Solid-State Circuits