Bit error rate analysis on iterative two-stage decoding of two dimensional codes by importance sampling
- T. Yamane
- Y. Katayama
- 2003
- ICC 2003
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48 results for Yasunao Katayama
An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability
- T. Yamane
- Y. Katayama
- 2003
- ICASSP 2003
Concatenation of Interleaved Binary/Non-binary Block Codes for Improved Forward Error Correction
- Y. Katayama
- T. Yamane
- 2003
- OFC 2003
On calculating interpolation polynomials for error values in Reed-Solomon decoding algorithm
- Yasunao Katayama
- Toshiyuki Yamane
- 2002
- ISIT 2002
One-shot Reed-Solomon decoding for high-performance dependable systems
- Yasunao Katayama
- Sumio Morioka
- 2001
- DSN 2001
O(log2m) iterative algorithm for multiplicative inversion in GF(2m)
- S. Morioka
- Y. Katayama
- 2000
- ISIT 2000
Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention
- Yasunao Katayama
- Eric J. Stuckey
- et al.
- 1999
- DFT 1999
Error evaluation algorithm for oneshot Reed-Solomon decoder
- Yasunao Katayama
- Sumio Morioka
- 1999
- ITCOM 1999
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Experimental 27 ns 1 Mb CMOS high-speed DRAM
- S. Dhong
- W.H. Henkels
- et al.
- 1989
- VLSI Circuits 1989