Implementation of a high speed multiport register file in a 1.8V, 0.25 μm CMOS bulk and SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
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42 results for W. Hwang
A 500-MHz, 32-word x 64-bit, eight-port self-resetting CMOS register file
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1998
- IEEE International SOI Conference 1998
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability
- W. Hwang
- G.D. Gristede
- et al.
- 1998
- CICC 1998
Pulse-to-static conversion latch with a self-timed control circuit
- W. Hwang
- R.V. Joshi
- et al.
- 1997
- ICCD 1997
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch
- W.H. Henkels
- W. Hwang
- et al.
- 1997
- VLSI Circuits 1997
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems
- Fang-Shi Lai
- Wei Hwang
- 1997
- IEEE Journal of Solid-State Circuits
Large-Signal 2T, 1C DRAM Cell: Signal and Layout Analysis
- W.H. Henkels
- W. Hwang
- 1994
- IEEE Journal of Solid-State Circuits
Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems
- F.S. Lai
- W. Hwang
- 1993
- VLSI-TSA 1993