Publications

2 results for Manabu Ohkubo

1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- - O. Takahashi
  - S. Dhong
  - et al.
- 2000
- ISSCC 2000
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- - Osamu Takahashi
  - Sang H. Dhong
  - et al.
- 2000
- IEEE Journal of Solid-State Circuits