(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
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9 results for Qingqing Liang
On the control of short-channel effect for MOSFETs with reverse halo implantation
- Huilong Zhu
- Huicai Zhong
- et al.
- 2007
- IEEE Electron Device Letters
On the systematic analysis of ring-delay performance using statistical behavior model
- Q. Liang
- B. Greene
- et al.
- 2009
- ISDRS 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
Optimizing history effects in 65nm PD-SOI CMOS
- Q. Liang
- T. Kawamura
- et al.
- 2006
- IEEE International SOI Conference 2006
An investigation of negative differential resistance and novel collector-current kink effects in SiGe HBTs operating at cryogenic temperatures
- Jiahui Yuan
- John D. Cressler
- et al.
- 2007
- IEEE Transactions on Electron Devices
Proton radiation effects in vertical SiGe HBTs fabricated on CMOS-compatible SOI
- Tianbing Chen
- Akil K. Sutton
- et al.
- 2005
- IEEE TNS