Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
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3 results for Z. Chen
High performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
- P. Smeys
- V. McGahay
- et al.
- 2000
- VLSI Technology 2000
A high performance 0.13 μm copper BEOL technology with low-k dielectric
- R.D. Goldblatt
- B.N. Agarwala
- et al.
- 2000
- IITC 2000