Line edge roughness and spacing effect on low-k TDDB characteristics
- F. Chen
- J.R. Lloyd
- et al.
- 2008
- IRPS 2008
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9 results for S. Sankaran
Development and optimization of porous pSiCOH interconnect dielectrics for 45 nm and beyond
- A. Grill
- S. Gates
- et al.
- 2008
- IITC 2008
Extendibility study of a PVD Cu seed process with Ar+ Rf-Plasma enhanced coverage for 45nm interconnects
- Andrew H. Simon
- Tibor Bolom
- et al.
- 2008
- MRS Spring Meeting 2008
Evaluation of Cu CMP barrier slurries for Ultra Low-k dielectric film (k~2.4) for 45nm technology
- Feng Zhao
- Laertis Economikos
- et al.
- 2007
- ICPT 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
A porous SiCOH dielectric with k=2.4 for high performance BEOL interconnects
- S. Gates
- A. Grill
- et al.
- 2006
- ADMETA 2006
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes
- T. Nogami
- S. Lane
- et al.
- 2005
- Optics East 2005
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002