A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- A. Rylyakov
- J. Tierno
- et al.
- 2008
- ISSCC 2008
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A 19gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS
- Didem Z. Turker
- Alexander Rylyakov
- et al.
- 2009
- VLSI Circuits 2009