Predicting and reducing substrate induced focus error
- Bernhard Liegl
- Brian Sapp
- et al.
- 2010
- SPIE Advanced Lithography 2010
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5 results for Chandrasekhar Sarma
32 NM Logic patterning options with immersion lithography
- K. Lai
- S. Burns
- et al.
- 2008
- SPIE Advanced Lithography 2008
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
A 0.18μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications
- A.R. Sitaram
- D.W. Abraham
- et al.
- 2003
- VLSI Technology 2003
Predicting substrate-induced focus error
- Bernhard Liegl
- Brian Sapp
- et al.
- 2010
- Journal of Micro/Nanolithography, MEMS, and MOEMS