Strain engineering for fully-depleted SOI devicesAli KhakifiroozPranita Kulkarniet al.2010ECS Transactions
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cellB. HaranA. Kumaret al.2008IEDM 2008
Access transistor design and optimization for 65/45nm high performance SOI eDRAMG. WangP. Parrieset al.2008VLSI-TSA 2008
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applicationsG. WangK. Chenget al.2006IEDM 2006
Direct silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOSHaizhou YinC.Y. Sunget al.2006IEDM 2006