A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
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5 results for Munir Naeem
FinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Plasma-etching processes for ULSI semiconductor circuits
- M. Armacost
- P.D. Hoh
- et al.
- 1999
- IBM J. Res. Dev
Thin-film temperature rise estimates during low energy ion bombardment in a plasma reactor
- M. Naeem
- D. Chidambarrao
- 1995
- Applied Physics Letters