A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
- Kyu-Hyoun Kim
- Daniel M. Dreps
- et al.
- 2009
- ISSCC 2009
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2 results for Frank D. Ferraiolo
A Clock Methodology for High-Performance Microprocessors
- Keith M. Carrig
- Albert M. Chu
- et al.
- 1997
- Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology