POWER7™, a highly parallel, scalable multi-core high end server processor
- Dieter F. Wendel
- Ron Kalla
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
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23 results for Daniel Dreps
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
- Robert Reutemann
- Michael Ruegg
- et al.
- 2010
- IEEE Journal of Solid-State Circuits
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- S. Voldman
- D. Hui
- et al.
- 2002
- Journal of Electrostatics