Gate leakage effects on yield and design considerations of PD/SOI SRAM designs
- Rouwaida Kanj
- Rajiv Joshi
- et al.
- 2007
- ISQED 2007
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7 results for Dhruva Acharyya
A test structure for characterizing local device mismatches
- Kanak Agarwal
- Frank Liu
- et al.
- 2006
- VLSI Circuits 2006
Triangulating to a defect's physical coordinates using multiple supply pad iDDQS: Test chip results
- Jim Plusquellic
- Dhruva Acharyya
- et al.
- 2006
- ISTFA 2006
Sensitivity analysis of quiescent signal analysis for defect detection
- Dhruva Acharyya
- Abhishek Singh
- et al.
- 2006
- DBT 2006
Rigorous extraction of process variations for 65-nm CMOS design
- Wei Zhao
- Frank Liu
- et al.
- 2009
- IEEE Trans Semicond Manuf
Design considerations for PD/SOI SRAM: Impact of gate leakage and threshold voltage variation
- Rouwaida Kanj
- Rajiv V. Joshi
- et al.
- 2008
- IEEE Trans Semicond Manuf
Quiescent-signal analysis: A multiple supply pad /DDQ method
- Jim Plusquellic
- Dhruva Acharyya
- et al.
- 2006
- IEEE Design and Test of Computers