Voltage ramp stress for bias temperature instability testing of metal-gate/high- k stacks
- Andreas Kerber
- Siddarth A. Krishnan
- et al.
- 2009
- IEEE Electron Device Letters
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31 results for Siddarth A. Krishnan
ALD TaN barrier for enhanced performance with low contact resistance for 14 nm Technology Node Cu Interconnects
- Joyeeta Nag
- Brian A. Cohen
- et al.
- 2015
- ECS Meeting 2015 Phoenix
Process optimizations for NBTI/PBTI for future replacement metal gate technologies
- Barry P. Linder
- A. Dasgupta
- et al.
- 2016
- IRPS 2016
Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond
- Takashi Ando
- B. Kannan
- et al.
- 2014
- VLSI Technology 2014
Metal Gate/High-κ dielectric gate stack reliability; or how i learned to live with trappy oxides
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- ECS Meeting 2013
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
Improving and optimizing reliability in future technologies with high-κ dielectrics
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- VLSI-DAT 2013
Improving and optimizing reliability in future technologies with high-κ dielectrics
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- VLSI-TSA 2013
Characterization and optimization of charge trapping in high-k dielectrics
- Eduard Cartier
- Takashi Ando
- et al.
- 2013
- IRPS 2013
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013