Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
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7 results for James Pan
Novel approach to reduce source/drain series and contact resistance in high-performance UTSOI CMOS devices using selective electrodeless CoWP or CoB process
- James Pan
- Anna Topol
- et al.
- 2007
- IEEE Electron Device Letters
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique
- James Pan
- Don Canaperi
- et al.
- 2004
- IEEE Electron Device Letters
Ultra-thin SOI CMOS using laser spike anneal
- Zhibin Ren
- J. Sleight
- et al.
- 2006
- VLSI-TSA 2006
Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005