High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
Publications
5 results for M. Hierlemann
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006