Intelligent interleaving of scenarios: A novel approach to system level test generation
- Shady Copty
- Itai Jaeger
- et al.
- 2007
- DAC 2007
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9 results for Itai Jaeger
A framework for the validation of processor architecture compliance
- Allon Adir
- Sigal Asaf
- et al.
- 2007
- DAC 2007
Harnessing machine learning to improve the success rate of stimuli generation
- Shai Fine
- Ari Freund
- et al.
- 2006
- IEEE TC
Addressing test generation challenges for configurable processor verification
- M. Rimon
- Yossi Lichtenstein
- et al.
- 2006
- HLDVT 2006
Constraint-based random stimuli generation for hardware verification
- Yehuda Naveli
- Michal Rimon
- et al.
- 2006
- AAAI/IAAI 2006
Harnessing machine learning to improve the success rate of stimuli generation
- Shai Fine
- Ari Freund
- et al.
- 2005
- HLDVT 2005
Reuse in system-level stimuli-generation
- Yoav Katz
- Itai Jaeger
- et al.
- 2005
- HLDVT 2005
Quality improvement methods for system-level stimuli generation
- Roy Emek
- Itai Jaeger
- et al.
- 2004
- ICCD 2004
Constraint-based random stimuli generation for hardware verification
- Yehuda Naveh
- Michal Rimon
- et al.
- 2007
- AI Magazine