Repeater Insertion combined with LGR methodology for on-chip interconnect timing optimization
- Michael Moreinis
- Arkadiy Morgenshtein
- et al.
- 2004
- ICECS 2004
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2 results for Michael Moreinis
Logic Gates as Repeaters (LGR) for area-efficient timing optimization
- Michael Moreinis
- Arkadiy Morgenshtein
- et al.
- 2006
- IEEE Transactions on VLSI Systems