A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2011
- CICC 2011
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38 results for Sergey V. Rylov
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011
Quarter-rate superconducting modulator for improved high resolution analog-to-digital converter
- Amol Inamdar
- Sergey Rylov
- et al.
- 2007
- IEEE TAS
A low power 10 Gb/s serial link transmitter in 90-nm CMOS
- Alexander Rylyakov
- Sergey Rylov
- 2005
- CSICS 2005
10+ Gb/s 90nm CMOS serial link demo in CBGA package
- Sergey Rylov
- Scott Reynolds
- et al.
- 2004
- CICC 2004
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
Static bipolar 11 GHz SiGe divider with 1V power supply
- Sergey Rylov
- Alexander Rylyakov
- 2003
- BCTM 2003
An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz
- Montek Singh
- Jose A. Tierno
- et al.
- 2002
- ASYNC 2002
Superconducting VLSI Logic Cell Library Using DC-Powered Clockless Dynamic SFQ Gates and ASIC-Style Layout Template
- Sergey Rylov
- Matthew Beck
- et al.
- 2023
- IEEE TAS
Clockless Dynamic SFQ and Gate With High Input Skew Tolerance
- Sergey V. Rylov
- 2019
- IEEE TAS