Publications

2 results for Peter Pfefferl

A 220-mm², four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- - Toshiaki Kirihata
  - Martin Gall
  - et al.
- 1998
- IEEE Journal of Solid-State Circuits
A 286 mm² 256 Mb DRAM with ×32 both-ends DQ
- - Yohji Watanabe
  - Hing Wong
  - et al.
- 1996
- IEICE Transactions on Electronics