Design considerations and implementations of a high performance dynamic register file
- R.V. Joshi
- W. Hwang
- 1999
- VLSID 1999
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210 results for Rajiv V. Joshi
A 500-MHz, 32-word x 64-bit, eight-port self-resetting CMOS register file
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
Implementation of a high speed multiport register file in a 1.8V, 0.25 μm CMOS bulk and SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1998
- IEEE International SOI Conference 1998
Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998
An analysis of the role of high energy neutral bombardment in longthrow/collimated sputtering of refractory metal barrier layers
- T. Smy
- R.V. Joshi
- et al.
- 1998
- Journal of Applied Physics
500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch
- W.H. Henkels
- W. Hwang
- et al.
- 1997
- VLSI Circuits 1997
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Pulse-to-static conversion latch with a self-timed control circuit
- W. Hwang
- R.V. Joshi
- et al.
- 1997
- ICCD 1997
Low temperature Al-Cu planarization by PVD Al-Cu-Ge alloys (Invited lecture)
- R.V. Joshi
- 1997
- Microelectronic Engineering