Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
- Subhendu Roy
- Mihir Choudhury
- et al.
- 2016
- IEEE TCADIS
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13 results for Mihir Choudhury
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
- Subhendu Roy
- Mihir Choudhury
- et al.
- 2014
- IEEE TCADIS
Low cost concurrent error masking using approximate logic circuits
- Mihir R. Choudhury
- Kartik Mohanram
- 2013
- IEEE TCADIS