Capacitive coupling based transient negative bit-line voltage (tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies
- S. Mukhopadhyay
- R.M. Rao
- et al.
- 2008
- ISCAS 2008
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30 results for Saibal Mukhopadhyay
Design and analysis of a self-repairing SRAM with on-chip monitor and compensation circuitry
- Niladri Narayan Mojumder
- Saibal Mukhopadhyay
- et al.
- 2008
- VTS 2008
An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Variability analysis for sub-100nm PD/SOI sense-amplifier
- Saibal Mukhopadhyay
- Rajiv V. Joshi
- et al.
- 2008
- ISQED 2008
Optimal dual-VT design in sub-100 nanometer PDSOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- VLSID 2008
Optimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Device design and optimization methodology for leakage and variability reduction in sub-45-nm FD/SOI SRAM
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Design and analysis of thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- ISLPED 2007
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
- Ching-Te Chuang
- Saibal Mukhopadhyay
- et al.
- 2007
- MTDT 2007
High-performance device optimization and dual-VT technology options for doublegate FET
- Aditya Bansal
- Keunwoo Kim
- et al.
- 2007
- ICICDT 2007