CMOS-compatible through silicon vias for 3D process integration
- Cornelia K. Tsang
- Paul S. Andry
- et al.
- 2006
- MRS Fall Meeting 2006
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61 results for Cornelia Tsang
System-on-Package (SOP) technology, characterization and applications
- J. Knickerbocker
- P. Andry
- et al.
- 2006
- ECTC 2006
Characterization of micro-bump C4 interconnects for Si-carrier SOP applications
- S.L. Wright
- R.J. Polastre
- et al.
- 2006
- ECTC 2006
Pb-free micro-joints (50 μm pitch) for the next generation micro-systems: The fabrication, assembly and characterization
- H. Gan
- S.L. Wright
- et al.
- 2006
- ECTC 2006
A CMOS-compatible process for fabricating electrical through-vias in silicon
- P. Andry
- C. Tsang
- et al.
- 2006
- ECTC 2006
Structure, design and process control for Cu bonded interconnects in 3D integrated circuits
- Kuan-Neng Chen
- Sang Hwui Lee
- et al.
- 2006
- IEDM 2006
Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ECTC 2005
Three-dimensional chip stack with integrated decoupling capacitors and thru-si via interconnects
- Bing Dang
- Michael Shapiro
- et al.
- 2010
- IEEE Electron Device Letters
Local measurements of flow boiling heat transfer on hot spots In 3D compatible radial microchannels
- Fanghao Yang
- Mark D. Schultz
- et al.
- 2015
- InterPACK 2015
Embedded two-phase cooling of large 3D compatible chips with radial channels
- Mark D. Schultz
- Fanghao Yang
- et al.
- 2015
- InterPACK 2015