Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
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3 results for K. Bandy
Junction profiling on hot carrier stressed device by dual lens electron holography and scanning capacitance microscopy
- Yun-Yu Wang
- J. Nxumalo
- et al.
- 2018
- IWJT 2018
Effect of hot carrier stress on device junctions measured by electron holography and scanning capacitance microscopy
- Yun-Yu Wang
- J. Nxumalo
- et al.
- 2018
- Applied Physics Letters