A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
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46 results for Jae-Joon Kim
Optimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- Microelectronics Journal
A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies
- Jae-Joon Kim
- Kaushik Roy
- 2006
- IEEE Transactions on VLSI Systems
A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations
- Chris Hyung-Il Kim
- Jae-Joon Kim
- et al.
- 2005
- IEEE Transactions on VLSI Systems
Double gate-MOSFET subthreshold circuit for ultralow power applications
- Jae-Joon Kim
- Kaushik Roy
- 2004
- IEEE Transactions on Electron Devices