22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Publications
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8 results for Geng Han
Line edge roughness reduction for 7nm metals
- Zheng Chen
- Steve McDermott
- et al.
- 2018
- SPIE Advanced Lithography 2018
EUV patterning successes and frontiers
- Nelson Felix
- Daniel Corliss
- et al.
- 2016
- SPIE Advanced Lithography 2016
Overcoming the challenges of 22-nm node patterning through litho-design co-optimization
- Martin Burkharde
- J.C. Arnold
- et al.
- 2009
- SPIE Advanced Lithography 2009
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield
- Aditya Bansal
- Rama N. Singh
- et al.
- 2008
- ICCD 2008
Challenges of implementing contour modeling in 32nm technology
- Daniel Fischer
- Geng Han
- et al.
- 2008
- SPIE Advanced Lithography 2008
32 NM Logic patterning options with immersion lithography
- K. Lai
- S. Burns
- et al.
- 2008
- SPIE Advanced Lithography 2008
Lithographic qualification of new opaque MoSi binary mask blank for the 32-nm node and beyond
- Greg McIntyre
- Michael Hibbs
- et al.
- 2010
- J. Micro/Nanolithogr. MEMS MOEMS