Technical visualizations in VLSI design
- P. Restle
- 2001
- DAC 2001
Publications
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66 results for Phillip Restle
When are transmission-line effects important for on-chip interconnections
- A. Deutsch
- G.V. Kopcsay
- et al.
- 1997
- ECTC 1997
Optimization of SiGe HBT Technology for High Speed Analog and Mixed-Signal Applications
- D.L. Harame
- J.M.C. Stork
- et al.
- 1993
- IEDM 1993
DRAM variable retention time
- P. Restle
- J.W. Park
- et al.
- 1992
- IEDM 1992
Low thermal budget antimony/phosphorus NMOS technology for CMOS
- D.L. Harame
- E. Ganin
- et al.
- 1991
- IEDM 1991
High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
- V.P. Kesan
- S. Subbana
- et al.
- 1991
- IEDM 1991
Deterministic Frequency and Voltage Enhancements on the POWER10 Processor
- Brian Vanderpool
- Phillip J. Restle
- et al.
- 2023
- IEEE JSSC
IBM z14: Processor characterization and power management for high-reliability mainframe systems
- Christopher Berry
- David Wolpert
- et al.
- 2019
- IEEE JSSC
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
A New “Shift and Ratio” Method for MOSFET Channel-Length Extraction
- Yuan Taur
- D.S. Zicherman
- et al.
- 1992
- IEEE Electron Device Letters