Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
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66 results for Phillip Restle
The clock distribution of the Power4 microprocessor
- Phillip J. Restle
- Craig A. Carter
- et al.
- 2002
- Digest of Technical Papers-IEEE International Solid-State Circuits Conference
The circuit and physical design of the POWER4 microprocessor
- J. Warnock
- J. Keaty
- et al.
- 2002
- IBM J. Res. Dev
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2002
- Proceedings of the Custom Integrated Circuits Conference
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
- Phillip J. Restle
- Albert E. Ruehli
- et al.
- 2001
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A clock distribution network for microprocessors
- Phillip J. Restle
- Timothy G. McNamara
- et al.
- 2001
- IEEE Journal of Solid-State Circuits
On-chip wiring design challenges for gigahertz operation operation
- Alina Deutsch
- Paul W. Coteus
- et al.
- 2001
- Proceedings of the IEEE
Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor
- P. Restle
- Keith A. Jenkins
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
When are transmission-line effects important for on-chip interconnections?
- Alina Deutsch
- Gerard V. Kopcsay
- et al.
- 1997
- IEEE T-MTT
A 400-MHz S/390 microprocessor
- Charles F. Webb
- Carl J. Anderson
- et al.
- 1997
- IEEE Journal of Solid-State Circuits