When are transmission-line effects important for on-chip interconnections
- A. Deutsch
- G.V. Kopcsay
- et al.
- 1997
- ECTC 1997
Publications
68 results for Phillip Restle
Design guidelines for short, medium, and long on-chip interconnections
- A. Deutsch
- W.D. Becker
- et al.
- 1996
- IEEE Topical Meeting EPEPS 1996
SiGe-Channel Heterojunction p-MOSFET’s
- Sophie Verdonckt-Vandebroek
- Bernard S. Meyerson
- et al.
- 1994
- IEEE Transactions on Electron Devices
Optimization of SiGe HBT Technology for High Speed Analog and Mixed-Signal Applications
- D.L. Harame
- J.M.C. Stork
- et al.
- 1993
- IEDM 1993
DRAM variable retention time
- P. Restle
- J.W. Park
- et al.
- 1992
- IEDM 1992
A New “Shift and Ratio” Method for MOSFET Channel-Length Extraction
- Yuan Taur
- D.S. Zicherman
- et al.
- 1992
- IEEE Electron Device Letters
Low thermal budget antimony/phosphorus NMOS technology for CMOS
- D.L. Harame
- E. Ganin
- et al.
- 1991
- IEDM 1991
High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
- V.P. Kesan
- S. Subbana
- et al.
- 1991
- IEDM 1991
Internal probing of submicron FETs and photoemission using individual oxide traps
- P. Restle
- Antonio Gnudi
- 1990
- IBM J. Res. Dev
Novel self-aligned W/TiN/TiSi2 contact structure for very shallow junctions and interconnections
- R.V. Joshi
- D. Moy
- et al.
- 1989
- Applied Physics Letters