A transregional CMOS SRAM with single, logic V DD and dynamic power rails
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2004
- VLSI Circuits 2004
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25 results for Y. Chan
High performance SRAMs in 1.5 V, 0.18μm partially depleted SOI technology
- R.V. Joshi
- A. Pellela
- et al.
- 2002
- VLSI Circuits 2002
2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 μm CMOS bulk technology
- R.V. Joshi
- S.P. Kowalczyk
- et al.
- 2000
- VLSI Circuits 2000
Picosecond Imaging Circuit Analysis of the IBM G6 Microprocessor Cache
- Moyra McManus
- Pia Sanda
- et al.
- 1999
- ISTFA 1999
Deep submicron design techniques for the 500MHz IBM S/390 G5 custom microprocessor
- D.E. Hoffman
- R.M. Averill
- et al.
- 1998
- ICCD 1998
High performance CMOS circuit techniques for the G-4 S/390 microprocessor
- J. Warnock
- L. Sigal
- et al.
- 1997
- ICCD 1997
15 Kb 1.5 ns Access on-chip tag SRAM
- P.F. Lu
- S.P. Kowalcyzk
- et al.
- 1997
- VLSI-TSA 1997
IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors
- David Wolpert
- E. Behnen
- et al.
- 2018
- IBM J. Res. Dev
IBM z13 circuit design and methodology
- J. Warnock
- Christopher Berry
- et al.
- 2015
- IBM J. Res. Dev
Circuit and physical design of the zenterprise™ ec12 microprocessor chips and multi-chip module
- James Warnock
- Yuen Chan
- et al.
- 2014
- IEEE Journal of Solid-State Circuits