Contact Cavity Shaping and Selective SiGe:B Low-Temperature Epitaxy Process Solution for sub 10-9 Ω.cm2 Contact Resistivity in Nonplanar FETs
- N. Breil
- B.-C. Lee
- et al.
- 2023
- VLSI Technology 2023
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7 results for Nicolas Breil
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
- Nicolas Breil
- A. Carr
- et al.
- 2017
- VLSI Technology 2017
Contacts in advanced CMOS: History and emerging challenges
- Christian Lavoie
- Praneet Adusumilli
- et al.
- 2017
- ECS Meeting 2017 - New Orleans
Formation and microstructure of thin Ti silicide films for advanced technologies
- Praneet Adusumilli
- A. Carr
- et al.
- 2016
- IITC/AMC 2016
Challenges in contact technologies for planar/non-planar Si technologies
- Praneet Adusumilli
- Emre Alptekin
- et al.
- 2014
- ECS Meeting 2014
Challenges of nickel silicidation in CMOS technologies
- Nicolas Breil
- Christian Lavoie
- et al.
- 2015
- Microelectronic Engineering