High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
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6 results for H. Van Meer
Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
- Nicolas Breil
- A. Carr
- et al.
- 2017
- VLSI Technology 2017
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- M. Cai
- B. Greene
- et al.
- 2008
- IEEE International SOI Conference 2008
Strain mapping of Si devices with stress memorization processing
- Y.Y. Wang
- John Bruley
- et al.
- 2013
- Applied Physics Letters
Novel high-performance analog devices for advanced low-power high-k metal gate complementary metal-oxide-semiconductor technology
- Jin-Ping Han
- Takashi Shimizu
- et al.
- 2011
- Japanese Journal of Applied Physics